As communication devices continue to shrink in size and increase in speed of operation, device manufacturers strive to design smaller, faster chips that consume less power and generate less heat. As the demand for speed and bandwidth increases and the chip size decreases, designers are faced with the difficult task of managing signal integrity. For example, designers try to account for signal propagation issues, such as signal skew, when designing communication devices where multiple signals are communicated across different signal propagation paths. Signal skew may occur when certain operational characteristics of a communication device, such as the length of a signal propagation path, affect the propagation times of one or more signals.
Signal propagation time may also be affected by other device parameters, such as fluctuating temperature, voltage, load, termination, etc. In some instances, manual signal alignment techniques are used to carefully match and balance delays of each signal path of a communication interface when attempting to account for signal propagation discrepancies. Many compensation techniques typically require prior knowledge obtained by simulation or measurement data which can be a time consuming and frustrating process. The simulation or measurement data may be used to approximate signal propagation variations and any associated skew as absolute delay or in terms of number and fractions of clock cycles for example. Designers thus face an onerous and unenviable task since each new design requires simulation and measuring to obtain new signal propagation data.
As described below, some communication interfaces include one or more “fly-by” or “daisy-chained” signals and one or more point-to-point signals (see FIGS. 1 and 2). For example, as shown in the communication interface of FIG. 2, one or more signal paths (DF-R0, DF-R1, DF-R2, etc.) may be described as being daisy-chained from a driver (DF) to multiple receivers (R0-R7), while other signal paths traverse in a point-to-point manner between a driver and particular receivers (D0-R0, D1-R1, D2-R2, etc.). This signal communication interface requires a designer to take into account the various signal propagation paths and other factors when communicating signals across the interface.
As shown in the Table below, signal propagation discrepancies can occur between the daisy-chained signals (DF-R0, DF-R1, DF-R2, etc.) and point-to-point signals (D0-R0, D1-R1, D2-R2, etc.). That is, signals communicated along point-to-point paths may arrive sooner or later than daisy-chained signals, which may result in signal skew. For instance, the distance from daisy-chained driver DF to receivers R0-R7 increases while distances from point-to-point drivers to respective receivers (D0-R0, D1-R1, D2-R2, etc.) change but not in the same amount and order. The Table below illustrates measured distances and delays associated with the topology of FIG. 2. The time column illustrates the time difference associated with signals propagated between (DF-Rx) and (Dx-Rx).
DF-RxDx-RxDelta (d)timeR0270 mm100 mm170 mm1.15 nsR1285 mm100 mm185 mm1.25 nsR2300 mm100 mm200 mm1.35 nsR3315 mm100 mm215 mm1.45 nsR4335 mm120 mm215 mm1.45 nsR5350 mm120 mm230 mm1.55 nsR6365 mm130 mm235 mm1.57 nsR7380 mm140 mm240 mm1.60 ns
FIG. 4 is a signal timing diagram which illustrates a case of false alignment during a conventional signal alignment process for a double data rate (DDR) type memory system. As shown in FIG. 4, a controlling device attempts a conventional signal alignment process to align a point-to-point signal (PPX0) and a fly-by clock signal (FBCK) as received by the device X. At step 1, the controlling device transmits the point-to-point signal (PPX0) to the device X after transmitting the FBCK. As part of the conventional alignments process, a comparison is made between the leading-edge of the received point-to-point signal (PPX0) and the leading-edge of the received FBCK. Based on the signal alignment protocol, the received signals are aligned when the time difference between the leading-edge of the received point-to-point signal (PPX0) and the leading-edge of the received FBCK are within a defined tolerance (tALGN).
Since the difference between the leading-edge of the received point-to-point signal (PPX0) and the leading-edge of the associated clock are not within the defined tolerance (tALGN) at step 1, at step 2, the controlling device transmits another point-to-point signal (PPX0) (incrementally delayed/advanced in time) and the signals are again compared at device X to determine if signal alignment is achieved. Since the difference between the leading-edge of the received point-to-point signal (PPX0) and the leading-edge of the associated clock are not within the defined tolerance (tALGN) at step 2, at step 3, the controlling device transmits yet another point-to-point signal (PPX0) (incrementally delayed/advanced) and the signals are again compared at device X to determine if signal alignment is achieved.
At step 3, the difference between the leading-edge of the received point-to-point signal (PPX0) and the leading-edge of the associated clock appear to be within the defined tolerance (tALGN), and the device X sends an acknowledging signal (PPX1) to the controlling device, acknowledging that the signals are aligned within the defined tolerance (tALGN). However, since the difference in propagation delay between the fly-by and point-to-point signal is greater than a clock period, the comparison included using the leading edge of an incorrect clock pulse at time 5′, resulting in a false alignment. The comparison should have used the leading edge of the clock at time 6′. Thus, the conventional signal alignment process breaks down if the difference in propagation delay between fly-by and point-to-point signal is greater than a clock period, resulting in the false alignment described above, and the subsequent false degree of confidence that communicated signals of the memory system are properly aligned.